Cadence M7000 Manual de usuario descargar pdf (Pagina 51)

Altera Corporation 51

MAX 7000 Programmable Logic Device Family Data Sheet

Tables 37 and 38 show the EPM7256S AC operating conditions.

Table 37. EPM7256S External Timing Parameters Note (1)

Symbol Parameter Conditions Speed Grade Unit

-7 -10 -15

MinMaxMinMaxMinMax

PD1

Input to non-registered output C1 = 35 pF 7.5 10.0 15.0 ns

PD2

I/O input to non-registered

output

C1 = 35 pF 7.5 10.0 15.0 ns

Global clock setup time 3.9 7.0 11.0 ns

Global clock hold time 0.0 0.0 0.0 ns

FSU

Global clock setup time of fast

input

3.0 3.0 3.0 ns

Global clock hold time of fast

input

0.0 0.5 0.0 ns

CO1

Global clock to output delay C1 = 35 pF 4.7 5.0 8.0 ns

Global clock high time 3.0 4.0 5.0 ns

Global clock low time 3.0 4.0 5.0 ns

ASU

Array clock setup time 0.8 2.0 4.0 ns

Array clock hold time 1.9 3.0 4.0 ns

ACO1

Array clock to output delay C1 = 35 pF 7.8 10.0 15.0 ns

ACH

Array clock high time 3.0 4.0 6.0 ns

ACL

Array clock low time 3.0 4.0 6.0 ns

CPPW

Minimum pulse width for clear

and preset

(2) 3.0 4.0 6.0 ns

ODH

Output data hold time after

clock

C1 = 35 pF (3) 1.0 1.0 1.0 ns

CNT

Minimum global clock period 7.8 10.0 13.0 ns

CNT

Maximum internal global clock

frequency

(4) 128.2 100.0 76.9 MHz

ACNT

Minimum array clock period 7.8 10.0 13.0 ns

ACNT

Maximum internal array clock

frequency

(4) 128.2 100.0 76.9 MHz

MAX

Maximum clock frequency (5) 166.7 125.0 100.0 MHz

1 2 ... 46 47 48 49 50 51 52 53 54 55 56 ... 65 66

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Cadence M7000 Manual de usuario Pagina 51

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