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Altera Corporation 5

MAX 7000 Programmable Logic Device Family Data Sheet

The MAX 7000 architecture supports 100% TTL emulation and

high-density integration of SSI, MSI, and LSI logic functions. The

MAX 7000 architecture easily integrates multiple devices ranging from

PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 7000 devices

are available in a wide range of packages, including PLCC, PGA, PQFP,

RQFP, and TQFP packages. See Table 5.

Notes:

(1) When the JTAG interface in MAX 7000S devices is used for either boundary-scan testing or for ISP, four I/O pins

become JTAG pins.

(2) Perform a complete thermal analysis before committing a design to this device package. For more information, see

the Operating Requirements for Altera Devices Data Sheet.

MAX 7000 devices use CMOS EEPROM cells to implement logic

functions. The user-configurable MAX 7000 architecture accommodates a

variety of independent combinatorial and sequential logic functions. The

devices can be reprogrammed for quick and efficient iterations during

design development and debug cycles, and can be programmed and

erased up to 100 times.

Table 5. MAX 7000 Maximum User I/O Pins Note (1)

Device 44-

PLCC

44-

PQFP

44-

TQFP

68-

PLCC

84-

PLCC

100-

PQFP

100-

TQFP

160-

PQFP

160-

PGA

192-

PGA

208-

PQFP

208-

RQFP

EPM7032 36 36 36

EPM7032S 36 36

EPM7064 36 36 52 68 68

EPM7064S 36 36 68 68

EPM7096 52 64 76

EPM7128E 68 84 100

EPM7128S 68 84 84 (2) 100

EPM7160E 64 84 104

EPM7160S 64 84 (2) 104

EPM7192E 124 124

EPM7192S 124

EPM7256E 132 (2) 164 164

EPM7256S 164 (2) 164

1 2 3 4 5 6 7 8 9 10 ... 65 66

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