Cadence Q DRIVE SERIES Manual de usuario descargar pdf (Pagina 2)

A. Synthesis

This tutorial introduces the basics of Cadence’s Synthesis and Timing Verification tool

(Ambit BuildGates Synthesis), and how to obtain a gate-level netlist from a Verilog RTL

code.

To learn more on Synthesis commands or scripts please refer to Synthesis and Timing

Verification Manual.

(i) Getting started

(a) First, make a directory called “synthesis” in your home directory.

(b) Generate the following Verilog RTL files pertinent to Figure 1 in the “synthesis”

directory.

In this figure:

The top-level module is my_design.v

The full adder module under my_design.v is full_adder.v

The 2-1 mux and flip-flop modules under my_design.v are mux.v and ff.v, respectively.

Note: all the Verilog RTL files related to Figure 1 are given in Appendix A.

my_design:

clk

bypass0

cin

bypass1

out_sum

out_cout

sel

wcout

wsum

full adder.v

mux.v

ff.v

wbypass1

wsel

wcin

wbypass0

Figure 1

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Cadence Q DRIVE SERIES Manual de usuario Pagina 2